1. Technical Field
The present invention relates to software tools in general, and, in particular, to a method within a software tool for verifying integrated circuit designs. Still more particularly, the present invention relates to a method within a software tool for determining fringing capacitances on single-layer and multi-layer on-chip passive devices.
2. Description of Related Art
On-chip passive devices can have a single or multiple back-end of the line (BEOL) metal layers. Currently, some foundry offers passive on-chip devices as a part of its design kits. Such passive on-chip devices can be spiral inductors (including multi-layer stacked inductors), transmission lines (microstrip and co-planar waveguide inter-connects including stacked metal line over a silicon substrate), bond pads and capacitors (MIM and vertically stacked parallel-plate). Each passive device is supported by schematic symbol, layout parameterized cell (Pcell), design rule checking (DRC), extraction and layout versus schematic (LVS) decks as well by a compact model that allows both time-domain and frequency-domain simulations such as parametric, temperature dependence and Monte-Carlo runs.
Whenever possible, it is very important to have analytical equations for the area, fringing and mutual capacitances of the on-chip passive devices. Although area capacitance calculations are usually quite straight-forward, the generation of analytical equations for fringing and mutual capacitances tends to be more difficult. Nevertheless, all capacitance terms (i.e., area, fringing and mutual) are required by any compact device model.
There are many drawbacks associated with the prior art methods of calculating fringing capacitance. For example, polynomial-based fringing capacitance equations are not always physically based; thus, the initial errors in polynomial fitting procedure can be relatively large, which may cause problems in accuracy and stability of a numerical convergence, etc. Consequently, it would be desirable to provide an improved method for determining fringing capacitances on on-chip passive devices.